1. Field of the Invention
The present invention relates to a fuse trimming circuit.
2. Description of the Related Art
In a semiconductor integrated circuit (IC), a fuse trimming circuit is used to improve output accuracy of internal circuits (e.g. Japanese Laid-Open Patent Application JP-P2000-133778A). FIG. 1 is a circuit diagram showing a conventional fuse trimming circuit. A fuse trimming circuit 10 has a CMOS (complementary metal-oxide semiconductor) input circuit 11, a fuse resistance 12, a trimming pad 13, a P-channel MOS transistor 14, and N-channel MOS transistors 15 and 16. The fuse resistance 12 can be blown out by application of voltage or current and pulls down the potential level at an input end of the CMOS input circuit 11 to a ground potential GND in the connection state. To the trimming pad 13, voltage or current for blowing out the fuse resistance 12 is supplied. The P-channel MOS transistor 14 pulls up the potential level at the input end of the CMOS input circuit 11 to supply potential VDD. The N-channel MOS transistors 15 and 16 is used for electrostatic protection.
The fuse resistance 12 is connected to the input end of the CMOS input circuit 11 at one end thereof and connected to a ground line GND at the other end thereof. The trimming pad 13 is connected to one end of the fuse resistance 12. The MOS transistor 14 is connected to the power line VDD at a source thereof, connected to the input end of the CMOS input circuit 11 at a drain thereof and connected to the ground line GND at a gate thereof. The MOS transistor 15 is connected to the power line VDD at a drain thereof, connected to the input end of the CMOS input circuit 11 at a source thereof and connected to the ground line GND at a gate thereof. The MOS transistor 16 is connected to the input end of the CMOS input circuit 11 at a drain thereof and connected to the ground line GND at source and gate thereof.
Since the fuse resistance 12 is not blown out in the fuse trimming circuit 10 when trimming is unnecessary, the input end of the CMOS input circuit 11 is fixed at the “L” level (GND potential). Since the fuse resistance 12 is blown out by supplying a predetermined voltage or current to the trimming pad 13 when trimming is necessary, the input end of the CMOS input circuit 11 is fixed at the “H” level (VDD potential).
In conjunction with the above description, Japanese Laid-Open Patent Application JP-P2000-236022A discloses a fuse trimming circuit. This fuse trimming circuit includes a pad terminal, a fuse resistance, a dividing resistance, a protection resistance, a protection NMOS transistor, a pulling-up transistor and an input circuit. The pad terminal is provided on a p-type semiconductor substrate and executes a trimming. The fuse resistance is connected to the pad terminal at one end thereof, and can be blown out. The dividing resistance is connected between another end of the fuse resistance and a ground line. The protection resistance is connected to the pad terminal at one end thereof. The protection NMOS transistor is connected to another end of the protection resistance at a drain thereof, connected to a ground at a source thereof and connected to a connection point between the fuse resistance and the dividing resistance at a gate thereof. The pulling-up transistor is connected to the protection resistance and is hung on a supply line for determining a potential level The input circuit is connected to the protection resistance at a gate thereof.
We have now discovered the facts as described below. In a display device for portable information appliances such as portable phones and personal digital assistants (PDA), when a circuit for driving a display panel is formed of an integrated circuit, a power supply circuit is generally installed in the IC chip. The power supply circuit is composed of a step-up circuit and a voltage regulator circuit. In the voltage regulator circuit including the power supply circuit, there has been demanded the accuracy of an output voltage of ±3% or within it. To meet the demand, an output of a reference voltage generation circuit composed of a band gap reference circuit (BGR) contained in the voltage regulator circuit is trimmed by using a fuse trimming circuit, thereby obtaining the output of the reference voltage generation circuit with high accuracy.
The IC chip for driving the display panel can be mounted on the display panel according to the chip on glass (COG) technology. The IC chip for the COG mounting is generally formed in the state where a gold bump is exposed on an input/output pad or a power supply pad. The IC chip is directly COG mounted in the state where the gold bump is exposed. For this reason, electrostatic discharge (ESD) surge could be applied to the gold bump exposed after the IC chip is mounted.
When the fuse trimming circuit 10 is applied to the above-mentioned band gap reference circuit of the IC chip and the IC chip is used for COG mounting, the below-mentioned problem occurs. In this case, the gold bump is also exposed on the trimming pad 13 of the fuse trimming circuit 10 and the IC chip is directly COG mounted with this gold bump being exposed. Trimming is performed in a wafer (a wafer state). The IC chip, in which the fuse resistance 12 is not blown out in the case that the trimming is unnecessary, is mounted. In the situation that the power line VDD and the ground line GND are connected to the supply potential VDD and the ground potential GND, respectively, after the IC chip is mounted, when ESD surge is applied to the gold bump exposed on the trimming pad 13 and an ESD surge current flows to the power line VDD and/or the ground line GND through the fuse resistance 12, there is a possibility that the fuse resistance 12 could be blown out depending on the dimension of the ESD surge and duration time.